Physical Design
Full floorplan-to-GDSII implementation across advanced process nodes.
- Floorplanning & power planning
- Placement, CTS & routing
- Hierarchical & flat flows
- ECO implementation
Services
Silicon expertise, from RTL to GDSII
Engage us for a single block or the full chip. Every service is delivered by senior engineers who work inside your flow.
What We Offer
Nine disciplines, one team
Logic Synthesis
RTL-to-gate synthesis tuned for power, performance and area.
- Logical & physical-aware synthesis
- SDC constraint development
- Multi-bit & clock-gating optimisation
- Formal equivalence checking (LEC)
Ultra Low Power Design
Multi-Vt, power gating, and dynamic voltage strategies for power-critical designs.
- UPF/CPF power intent
- Power gating & retention
- DVFS & multi-voltage domains
- Leakage & dynamic power reduction
DFT & BIST
Test architecture, implementation and on-chip self-test for high coverage and low test cost.
- Scan insertion, compression & ATPG
- Memory BIST (MBIST) with repair & Logic BIST (LBIST)
- JTAG / IEEE 1149.1 & 1687 (IJTAG)
- In-field test for automotive (ISO 26262)
Analog Custom Design
Custom analog and mixed-signal IP, from specification and schematic to verified layout.
- Power management: LDOs, DC-DC, bandgaps
- PLLs, DLLs & clock generation
- Data converters, I/Os & sensors
- Custom layout, extraction & post-layout sim
Timing Closure
STA-driven optimisation to meet tight setup and hold margins at speed.
- Multi-mode multi-corner STA
- Constraint development & review
- OCV / AOCV / POCV analysis
- Signal integrity & crosstalk fixing
Tapeout Support
Sign-off checks, DRC/LVS, and foundry coordination through to tapeout.
- Physical verification (DRC/LVS/ERC)
- IR drop & EM analysis
- Foundry & OSAT coordination
- Tapeout checklists & reviews
Design Verification
Formal and simulation-based verification to ensure functional correctness.
- UVM testbench development
- Formal property verification
- Coverage closure
- Gate-level simulation
Library Characterisation
Timing, power, and noise characterisation of standard cell and custom IP libraries across PVT corners.
- Liberty (.lib) generation
- CCS / ECSM models
- PVT corner sweeps
- Library QA & validation
How We Work
A simple engagement model
01Discovery — we review your spec, flow and schedule.
02Plan — scope, milestones and team agreed up front.
03Execute — embedded in your EDA environment.
04Sign-off — handover through to tapeout.
Have a project in mind?
Tell us your node, schedule and challenge — we'll suggest the right engagement.
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